The present inventive concept relates generally to shift register circuits. More particularly, the inventive concept relates to a shift register adapted for use within a semiconductor memory device such as a dynamic random access memory (DRAM) or the like.
The DRAM is one type of volatile memory including a great plurality of memory cells. Each memory cell is implemented with one access transistor and a corresponding storage capacitor. Because the DRAM is volatile in its data storage capabilities, a refresh operation must be applied to the memory cells. The DRAM is commonly used as a main memory within an electronic system because it provides high data access (read/write) speeds and may be very densely integrated to yield a large capacity memory in a relatively small size.
High-performance DRAMs provide improved operating speed, and include the Synchronous DRAM (SDRAM), the Double Data Rate (DDR) SDRAM, and the Fast Cycle RAM (FCRAM). Of these, the SDRAM enables clock synchronous data access at the rising edge or falling edge of the controlling clock. In contrast, the DDR SDRAM enables clock synchronous data access at both the rising and falling edges of the clock. So, in general, the DDR SDRAM operates at a data transmission rate twice (2×) that of an analogous SDRAM.
Many types of semiconductor memory devices, including the SDRAM, DDR SDRAM and/or FCRAM, commonly incorporate a shift register implemented by a plurality of flip-flops. The shift register is used to provide circuit defining a write latency (WL) and/or a read latency (RL).
Because operation of the shift register (i.e., the plurality of flip-flops) consumes significant power, some power-saving modes of operation (e.g., a power-down mode, sleep mode, wait mode, etc.) for the constituent semiconductor memory device reduce power consumption by turning off a controlling (or toggling) clock applied to the plurality of flip-flops. However, it is important to note that if input data is applied to the shift register during a power-saving mode, the toggling clock must immediately be restored. This re-application of the toggling clock is typically accomplished by having the semiconductor memory device enter an active mode of operation (e.g. a wake-up mode).
Of further note, the transition between a power-saving mode and an active mode may cause stray or errant flip-flop toggling or ill-clocked data shifts (hereafter, generically referred to a “glitch”) within the shift register. Such “glitching” can generate erroneous control signals or control signal timing during a data access operation. Therefore, it is important to prevent the generation of a glitch in the operation of the shift register. In other words, when a glitch occurs in the clock controlling operation of the shift register, it is difficult to properly shift data. Thus, it is highly desirable to provide a shift register capable of a glitch-free operation even when said shift register transitions between power-saving and active modes of operation.